Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA

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Main Authors: Berta Pallerols Mir, Rubén D. López Noa, Roger Rivero Labrada, Alexander Suárez Léon, Danelia Matos Molina
Format: Article
Language:Spanish
Published: Instituto Superior Politécnico José Antonio Echeverría (CUJAE) 2010-09-01
Series:Revista Ingeniería Electrónica, Automática y Comunicaciones
Online Access:http://rielac.cujae.edu.cu/index.php/rieac/article/view/44
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author Berta Pallerols Mir
Rubén D. López Noa
Roger Rivero Labrada
Alexander Suárez Léon
Danelia Matos Molina
spellingShingle Berta Pallerols Mir
Rubén D. López Noa
Roger Rivero Labrada
Alexander Suárez Léon
Danelia Matos Molina
Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
Revista Ingeniería Electrónica, Automática y Comunicaciones
author_facet Berta Pallerols Mir
Rubén D. López Noa
Roger Rivero Labrada
Alexander Suárez Léon
Danelia Matos Molina
author_sort Berta Pallerols Mir
title Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
title_short Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
title_full Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
title_fullStr Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
title_full_unstemmed Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGA
title_sort módulo de interfaz para cuatro lámparas de siete - segmentos en fpga
publisher Instituto Superior Politécnico José Antonio Echeverría (CUJAE)
series Revista Ingeniería Electrónica, Automática y Comunicaciones
issn 1815-5928
publishDate 2010-09-01
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mso-fareast-font-family:"Times New Roman"; mso-ansi-language:ES; mso-fareast-language:ES;} span.TextonormalCar {mso-style-name:"Texto normal Car"; mso-style-unhide:no; mso-style-locked:yes; mso-style-link:"Texto normal"; mso-ansi-language:ES; mso-fareast-language:ES;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; font-size:10.0pt; mso-ansi-font-size:10.0pt; mso-bidi-font-size:10.0pt;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} --> <!--[if gte mso 10]> <style>&#13; /* Style Definitions */&#13; table.MsoNormalTable&#13; {mso-style-name:"Tabla normal";&#13; mso-tstyle-rowband-size:0;&#13; mso-tstyle-colband-size:0;&#13; mso-style-noshow:yes;&#13; mso-style-priority:99;&#13; mso-style-qformat:yes;&#13; mso-style-parent:"";&#13; mso-padding-alt:0cm 5.4pt 0cm 5.4pt;&#13; mso-para-margin:0cm;&#13; mso-para-margin-bottom:.0001pt;&#13; mso-pagination:widow-orphan;&#13; font-size:11.0pt;&#13; font-family:"Calibri","sans-serif";&#13; mso-ascii-font-family:Calibri;&#13; mso-ascii-theme-font:minor-latin;&#13; mso-fareast-font-family:"Times New Roman";&#13; mso-fareast-theme-font:minor-fareast;&#13; mso-hansi-font-family:Calibri;&#13; mso-hansi-theme-font:minor-latin;&#13; mso-bidi-font-family:"Times New Roman";&#13; mso-bidi-theme-font:minor-bidi;}&#13; </style> <![endif]--> <p class="Textonormal"><span lang="ES">El presente artículo expone el diseño, síntesis e implementación sobre FPGA de un circuito digital para el manejo mediante visualización multiplexada de cuatro lámparas de siete segmentos. Se describe el principio de funcionamiento y se detalla el diseño de los bloques funcionales principales que componen el circuito. Se especifican los recursos asignados en la implementación para un FPGA específico y se analiza la respuesta en frecuencia del diseño. Finalmente se muestran y discuten los resultados de una simulación post implementación y<span>  </span>se valora la utilidad y posibles aplicaciones del dispositivo.</span></p>
url http://rielac.cujae.edu.cu/index.php/rieac/article/view/44
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spelling doaj-eb594fb1efaa4dd3a581ea8e585019b72020-11-25T00:11:18ZspaInstituto Superior Politécnico José Antonio Echeverría (CUJAE) Revista Ingeniería Electrónica, Automática y Comunicaciones1815-59282010-09-01301374410.1234/rielac.v30i1.44Módulo de interfaz para cuatro lámparas de siete - segmentos en FPGABerta Pallerols MirRubén D. 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mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif"; mso-fareast-font-family:"Times New Roman"; mso-ansi-language:ES; mso-fareast-language:ES;} span.TextonormalCar {mso-style-name:"Texto normal Car"; mso-style-unhide:no; mso-style-locked:yes; mso-style-link:"Texto normal"; mso-ansi-language:ES; mso-fareast-language:ES;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; font-size:10.0pt; mso-ansi-font-size:10.0pt; mso-bidi-font-size:10.0pt;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} --> <!--[if gte mso 10]> <style>&#13; /* Style Definitions */&#13; table.MsoNormalTable&#13; {mso-style-name:"Tabla normal";&#13; mso-tstyle-rowband-size:0;&#13; mso-tstyle-colband-size:0;&#13; mso-style-noshow:yes;&#13; mso-style-priority:99;&#13; mso-style-qformat:yes;&#13; mso-style-parent:"";&#13; mso-padding-alt:0cm 5.4pt 0cm 5.4pt;&#13; mso-para-margin:0cm;&#13; mso-para-margin-bottom:.0001pt;&#13; mso-pagination:widow-orphan;&#13; font-size:11.0pt;&#13; font-family:"Calibri","sans-serif";&#13; mso-ascii-font-family:Calibri;&#13; mso-ascii-theme-font:minor-latin;&#13; mso-fareast-font-family:"Times New Roman";&#13; mso-fareast-theme-font:minor-fareast;&#13; mso-hansi-font-family:Calibri;&#13; mso-hansi-theme-font:minor-latin;&#13; mso-bidi-font-family:"Times New Roman";&#13; mso-bidi-theme-font:minor-bidi;}&#13; </style> <![endif]--> <p class="Textonormal"><span lang="ES">El presente artículo expone el diseño, síntesis e implementación sobre FPGA de un circuito digital para el manejo mediante visualización multiplexada de cuatro lámparas de siete segmentos. Se describe el principio de funcionamiento y se detalla el diseño de los bloques funcionales principales que componen el circuito. Se especifican los recursos asignados en la implementación para un FPGA específico y se analiza la respuesta en frecuencia del diseño. Finalmente se muestran y discuten los resultados de una simulación post implementación y<span>  </span>se valora la utilidad y posibles aplicaciones del dispositivo.</span></p>http://rielac.cujae.edu.cu/index.php/rieac/article/view/44