A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used...

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Bibliographic Details
Main Authors:	Yunrui Zhao, Zhiming Chen, Zicheng Liu, Xiaoran Li, Xinghua Wang
Format:	Article
Language:	English
Published:	MDPI AG 2020-10-01
Series:	Electronics
Subjects:	CMOS high speed counter prescaler TSPC multi-modulus-divider
Online Access:	https://www.mdpi.com/2079-9292/9/11/1773

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spelling	doaj-ea4a14ad84064ce9ba775de4c9acdfdc2020-11-25T03:58:31ZengMDPI AGElectronics2079-92922020-10-0191773177310.3390/electronics9111773A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency SynthesizerYunrui Zhao0Zhiming Chen1Zicheng Liu2Xiaoran Li3Xinghua Wang4School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing 100081, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing 100081, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing 100081, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing 100081, ChinaHigh speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.https://www.mdpi.com/2079-9292/9/11/1773CMOShigh speedcounterprescalerTSPCmulti-modulus-divider
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Yunrui Zhao Zhiming Chen Zicheng Liu Xiaoran Li Xinghua Wang
spellingShingle	Yunrui Zhao Zhiming Chen Zicheng Liu Xiaoran Li Xinghua Wang A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer Electronics CMOS high speed counter prescaler TSPC multi-modulus-divider
author_facet	Yunrui Zhao Zhiming Chen Zicheng Liu Xiaoran Li Xinghua Wang
author_sort	Yunrui Zhao
title	A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
title_short	A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
title_full	A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
title_fullStr	A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
title_full_unstemmed	A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
title_sort	4.1 ghz–9.2 ghz programmable frequency divider for ka band pll frequency synthesizer
publisher	MDPI AG
series	Electronics
issn	2079-9292
publishDate	2020-10-01
description	High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.
topic	CMOS high speed counter prescaler TSPC multi-modulus-divider
url	https://www.mdpi.com/2079-9292/9/11/1773
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A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

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