Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory

• Main Authors: Tao Yang, Zhiliang Xia, Dandan Shi, Yingjie Ouyang, Zongliang Huo
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: Lognormal distribution; 3D NAND; polysilicon channel; grain size
• Online Access: https://ieeexplore.ieee.org/document/8976155/
• ISSN: 2168-6734

The impact of linear correlation between lognormal distribution grain size mean and sigma along the polysilicon channel on threshold voltage (Vth) variability has been investigated in three dimensional (3D) NAND flash. The variety of grain size mean and sigma results in the unstable Vth variability. To obtain a stable Vth distribution with various grain size mean, the grain size mean dependent Vth variability sensitivity to the grain size sigma was used to optimize the linear correlation between grain size mean and sigma via TCAD simulation. The optimized linear correlation with stable Vth variability is obtained except for the “unbalance region” affected by the combination of grain boundaries and positions with these grain size mean and sigma values resulting in the slightly shrinking Vth variability. Our results strongly suggest that this approach could guide the direction of polysilicon crystallization optimization to obtain stable Vth distribution with the predicted linear correlation between grain size mean and sigma.