On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX <roman>s</roman>/DEMUX <roman>s</roman> With 40-GH <roman>z</roman> Channel Bandwidth

• Main Authors: S. Papaioannou, D. Fitsios, G. Dabos, K. Vyrsokinos, G. Giannoulis, A. Prinzen, C. Porschatis, M. Waldow, D. Apostolopoulos, H. Avramopoulos, N. Pleros
• Format: Article
• Language: English
• Published: IEEE 2015-01-01
• Series: IEEE Photonics Journal
• Subjects: Dense wavelength division multiplexing (DWDM); micro-ring resonators; optical interconnects; silicon multiplexer; silicon-on-insulator (SOI)
• Online Access: https://ieeexplore.ieee.org/document/6987249/

We demonstrate two 8 &#x00D7; 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being ~12 and ~9 &#x03BC;m, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 &#x03BC;W/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than 18 dB crosstalk and higher than 40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 &#x00D7; 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties.