Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operati...

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Bibliographic Details
Main Authors: Gianluca Giustolisi, Gaetano Palumbo
Format: Article
Language:English
Published: MDPI AG 2021-03-01
Series:Electronics
Subjects:
settling time
design optimization
operational amplifiers
three-stage amplifiers
feedback amplifiers
low-voltage
Online Access:https://www.mdpi.com/2079-9292/10/5/612
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spelling doaj-e8f5c754a1cf4e74a9fa28d3228324982021-03-07T00:00:06ZengMDPI AGElectronics2079-92922021-03-011061261210.3390/electronics10050612Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal BehaviorGianluca Giustolisi0Gaetano Palumbo1Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), Università degli Studi di CataniaViale A., I-95125 Catania, ItalyDipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), Università degli Studi di CataniaViale A., I-95125 Catania, ItalyAn analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.https://www.mdpi.com/2079-9292/10/5/612settling timedesign optimizationoperational amplifiersthree-stage amplifiersfeedback amplifierslow-voltage
collection DOAJ
language English
format Article
sources DOAJ
author Gianluca Giustolisi
Gaetano Palumbo
spellingShingle Gianluca Giustolisi
Gaetano Palumbo
Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
Electronics
settling time
design optimization
operational amplifiers
three-stage amplifiers
feedback amplifiers
low-voltage
author_facet Gianluca Giustolisi
Gaetano Palumbo
author_sort Gianluca Giustolisi
title Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
title_short Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
title_full Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
title_fullStr Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
title_full_unstemmed Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior
title_sort efficient design strategy for optimizing the settling time in three-stage amplifiers including small- and large-signal behavior
publisher MDPI AG
series Electronics
issn 2079-9292
publishDate 2021-03-01
description An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.
topic settling time
design optimization
operational amplifiers
three-stage amplifiers
feedback amplifiers
low-voltage
url https://www.mdpi.com/2079-9292/10/5/612
work_keys_str_mv AT gianlucagiustolisi efficientdesignstrategyforoptimizingthesettlingtimeinthreestageamplifiersincludingsmallandlargesignalbehavior
AT gaetanopalumbo efficientdesignstrategyforoptimizingthesettlingtimeinthreestageamplifiersincludingsmallandlargesignalbehavior
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