Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era
In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-Vdd/frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targete...
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doaj-e8838775bc0b4a1d8f668f417739c83e2021-03-29T22:50:08ZengIEEEIEEE Access2169-35362019-01-017331153312910.1109/ACCESS.2019.29004778648367Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon EraSohaib Majzoub0https://orcid.org/0000-0003-3196-2635Resve A. Saleh1Imran Ashraf2Mottaqiallah Taouil3Said Hamdioui4Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab EmiratesDepartment of Electrical and Computer Engineering, The University of British Columbia, Vancouver, CanadaLaboratory of Computer Engineering, Delft University of Technology, Delft, The NetherlandsLaboratory of Computer Engineering, Delft University of Technology, Delft, The NetherlandsLaboratory of Computer Engineering, Delft University of Technology, Delft, The NetherlandsIn this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-Vdd/frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-Vdd/frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-Vdd/frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-Vdd/frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.https://ieeexplore.ieee.org/document/8648367/3D-stacked chipdark-silicondynamic powerenergy-delay-productfrequency scalingidle power |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Sohaib Majzoub Resve A. Saleh Imran Ashraf Mottaqiallah Taouil Said Hamdioui |
spellingShingle |
Sohaib Majzoub Resve A. Saleh Imran Ashraf Mottaqiallah Taouil Said Hamdioui Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era IEEE Access 3D-stacked chip dark-silicon dynamic power energy-delay-product frequency scaling idle power |
author_facet |
Sohaib Majzoub Resve A. Saleh Imran Ashraf Mottaqiallah Taouil Said Hamdioui |
author_sort |
Sohaib Majzoub |
title |
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era |
title_short |
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era |
title_full |
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era |
title_fullStr |
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era |
title_full_unstemmed |
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era |
title_sort |
energy optimization for large-scale 3d manycores in the dark-silicon era |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2019-01-01 |
description |
In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-Vdd/frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-Vdd/frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-Vdd/frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-Vdd/frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice. |
topic |
3D-stacked chip dark-silicon dynamic power energy-delay-product frequency scaling idle power |
url |
https://ieeexplore.ieee.org/document/8648367/ |
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