Purwarupa Perangkat Keras untuk Eksekusi Algoritma AES Berbasis FPGA

• Main Authors: Nia Gella Augoestien, Agfianto Eko Putra
• Format: Article
• Language: Indonesian
• Published: Universitas Gadjah Mada 2015-10-01
• Series: IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)
• Subjects: AES Algorithm, FPGA, resource sharing, iterative, pipeline
• Online Access: https://jurnal.ugm.ac.id/ijeis/article/view/7644

AES cryptography algorithm is a tool which often using to protect confidentiality of data.Confidentiality of data is principle parameter of data security in various system. Data security achieve by collaborated AES algorithm with another cryptosystem tools. Therefore, limited resource hardware to excecuteAES algorithm is very important.             This research proposed hardware prototype for excecuting AES algorithm based on FPGA. Optimumresource utilizing become basic priority in this design. So that, we are using resource sharing between hardware for encryption and decryption, iteratif architecture on round level, pipeline architecture on transformation level with 32-bit architecture at design to attain optimum resource utilizing.             Hardware prototype in this research use FPGA Xilinx Spartan®-6 (XC6LX16-CS324), encryption and decryption have been done in this hardware prototype. This prototype have 1,94Mbps/Slice hardware efficiency, 308,96Mbps throughput with only using 6% resource that available on this FPGA.