A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compa...

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Main Authors: Nabihah Ahmad, Rezaul Hasan
Format: Article
Language:English
Published: Hindawi Limited 2013-01-01
Series:Active and Passive Electronic Components
Online Access:http://dx.doi.org/10.1155/2013/148518
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spelling doaj-e505fbf5ba4c410da98a8e5864aed96e2020-11-24T22:17:16ZengHindawi LimitedActive and Passive Electronic Components0882-75161563-50312013-01-01201310.1155/2013/148518148518A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOSNabihah Ahmad0Rezaul Hasan1Center for Research in Analog and VLSI microsystem Design (CRAVE), School of Engineering and Advanced Technology (SEAT), Massey University, Auckland 0632, New ZealandCenter for Research in Analog and VLSI microsystem Design (CRAVE), School of Engineering and Advanced Technology (SEAT), Massey University, Auckland 0632, New ZealandA power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.http://dx.doi.org/10.1155/2013/148518
collection DOAJ
language English
format Article
sources DOAJ
author Nabihah Ahmad
Rezaul Hasan
spellingShingle Nabihah Ahmad
Rezaul Hasan
A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
Active and Passive Electronic Components
author_facet Nabihah Ahmad
Rezaul Hasan
author_sort Nabihah Ahmad
title A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
title_short A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
title_full A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
title_fullStr A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
title_full_unstemmed A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
title_sort 0.8 v 0.23 nw 1.5 ns full-swing pass-transistor xor gate in 130 nm cmos
publisher Hindawi Limited
series Active and Passive Electronic Components
issn 0882-7516
1563-5031
publishDate 2013-01-01
description A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.
url http://dx.doi.org/10.1155/2013/148518
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