A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip
This paper introduces a small-area, low-power delta-sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three-stage cascaded half-band filter is utilized. An optimized sturdy MASH ΔΣ modulator was used to avoid instability caused by high-...
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2021-01-01
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Series: | Journal of Sensors |
Online Access: | http://dx.doi.org/10.1155/2021/6630100 |
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doaj-e228948948804685a6a70cf5b7a55c6b2021-06-07T02:12:32ZengHindawi LimitedJournal of Sensors1687-72682021-01-01202110.1155/2021/6630100A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific ChipPeng Li0Wei Xi1Xiangjun Zeng2Xiaobo Li3Dandan Zheng4Digital Grid Research InstituteDigital Grid Research InstituteSchool of Electrical and Information EngineeringDigital Grid Research InstituteHangzhou Sec-Chip Technology Co.This paper introduces a small-area, low-power delta-sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three-stage cascaded half-band filter is utilized. An optimized sturdy MASH ΔΣ modulator was used to avoid instability caused by high-order shaping and reduce the area at the same time. The postanalog reconstruction includes a switched-capacitor DAC (SC DAC) and a 4-tap FIR/IIR hybrid filter, which not only meets the requirements of low power but also promotes the out-of-band SNR. The final chip is fabricated in a 55 nm CMOS process, occupies 0.08 mm2, and consumes 1.5 mW of analog power at 2.5 V supply. The simulation results show that the dynamic range is 85.7 dB, while the out-of-band SNR is 40.5 dB.http://dx.doi.org/10.1155/2021/6630100 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Peng Li Wei Xi Xiangjun Zeng Xiaobo Li Dandan Zheng |
spellingShingle |
Peng Li Wei Xi Xiangjun Zeng Xiaobo Li Dandan Zheng A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip Journal of Sensors |
author_facet |
Peng Li Wei Xi Xiangjun Zeng Xiaobo Li Dandan Zheng |
author_sort |
Peng Li |
title |
A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip |
title_short |
A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip |
title_full |
A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip |
title_fullStr |
A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip |
title_full_unstemmed |
A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip |
title_sort |
small-area, low-power delta-sigma dac applied to a power-specific chip |
publisher |
Hindawi Limited |
series |
Journal of Sensors |
issn |
1687-7268 |
publishDate |
2021-01-01 |
description |
This paper introduces a small-area, low-power delta-sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three-stage cascaded half-band filter is utilized. An optimized sturdy MASH ΔΣ modulator was used to avoid instability caused by high-order shaping and reduce the area at the same time. The postanalog reconstruction includes a switched-capacitor DAC (SC DAC) and a 4-tap FIR/IIR hybrid filter, which not only meets the requirements of low power but also promotes the out-of-band SNR. The final chip is fabricated in a 55 nm CMOS process, occupies 0.08 mm2, and consumes 1.5 mW of analog power at 2.5 V supply. The simulation results show that the dynamic range is 85.7 dB, while the out-of-band SNR is 40.5 dB. |
url |
http://dx.doi.org/10.1155/2021/6630100 |
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