| Summary: | Integrated circuit (IC) fabrication technology has improved to 7 nm resulting that IC can accommodate more transistors to implement system-on-a-chip (SOC). SOC generally consists of a great quantity digital circuits with specific functions. Diverse signals not only convey inside but also communicate outside among circuits. For hundreds of thousands interlaced and complicated signals, it is an extreme big challenge to route in shrink channel. In this work, we propose a complexity effect routing algorithm based on the Lee algorithm to achieve fast verification for SOC. The advantages are to gain fast evaluated for various architectures of route, trace path from origin to destination and set diverse complexity to simulate SOC architectures. Experimental results demonstrate the achievements on five complexity sets of routing benchmarks. Keywords: Complexity effect, Routing, SOC, VLSI
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