A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

• Main Authors: Lei Luo, Zhiqun Li, Yan Yao, Guoxiao Cheng
• Format: Article
• Language: English
• Published: MDPI AG 2019-10-01
• Series: Electronics
• Subjects: digital step attenuator; low phase variation; triple well isolation nmos; wideband; cmos integrated circuits
• Online Access: https://www.mdpi.com/2079-9292/8/10/1149
• ISSN: 2079-9292

A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99−9.33 dB; the maximum relative attenuation is 31.87−30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58−0.36 dB and the phase error RMS is 2.06−3.46° in the 12−17 GHz frequency range. The total chip area is 1 × 0.9 mm².