Designing an Efficient WCDMA Compliant Fractional-N Frequency Synthesizer
In this paper, fractional-N PLL is introduced to generate 1.965 GHz according to WCDMA specification , where a proposed deterministic 4th order MASH structure that guarantees a long sequence length to be used with simple stochastic dithering at the last stage as a noise shaping technique achieving...
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| Format: | Article |
| Language: | English |
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Al-Nahrain Journal for Engineering Sciences
2015-01-01
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| Series: | مجلة النهرين للعلوم الهندسية |
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| Online Access: | https://nahje.com/index.php/main/article/view/149 |
| Summary: | In this paper, fractional-N PLL is introduced to generate 1.965 GHz according to WCDMA specification , where a proposed deterministic 4th order MASH structure that guarantees a long sequence length to be used with simple stochastic dithering at the last stage as a noise shaping technique achieving hardware budget compared with classical dithering that used long linear feedback shift register LFSR . Modulator in band phase noise is -100dBc/Hz within the loop bandwidth of 1MHz, the PLL lock time is less than 25 μs. C++ language is used in the simulation of the system behavior for all blocks of the synthesizer due to its flexibility and high speed of execution, then data is post processed using MATLAB R2011a.
The proposed MASH structure consumes 89% FFs and 90% LUTs of the Dithered MASH reported in ref.[9] for identical number of bits achieve significant hardware cost reduction .
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| ISSN: | 2521-9154 2521-9162 |