A heuristic fault based optimization approach to reduce test vectors count in VLSI testing
In this work we have proposed a heuristic approach to reduce the test vector count during VLSI testing of standard ISCAS circuits. With the shrinking die-space and increasing circuitry on a single Integrated circuit, the number of test vectors required for testing is also increasing. The number of t...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2019-04-01
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| Series: | Journal of King Saud University: Computer and Information Sciences |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1319157817300423 |