Visual software system for memory interleaving simulation

• Main Authors: Milenković Katarina, Stanisavljević Žarko, Đorđević Jovan
• Format: Article
• Language: English
• Published: Faculty of Technical Sciences in Cacak 2017-01-01
• Series: Serbian Journal of Electrical Engineering
• Subjects: computer architecture and organization; memory interleaving; software system; simulation; main memory; random-access memory; laboratory exercise
• Online Access: http://www.doiserbia.nb.rs/img/doi/1451-4869/2017/1451-48691701051M.pdf
• ISSN: 1451-4869; 2217-7183

This paper describes the visual software system for memory interleaving simulation (VSMIS), implemented for the purpose of the course Computer Architecture and Organization 1, at the School of Electrical Engineering, University of Belgrade. The simulator enables students to expand their knowledge through practical work in the laboratory, as well as through independent work at home. VSMIS gives users the possibility to initialize parts of the system and to control simulation steps. The user has the ability to monitor simulation through graphical representation. It is possible to navigate through the entire hierarchy of the system using simple navigation. During the simulation the user can observe and set the values of the memory location. At any time, the user can reset the simulation of the system and observe it for different memory states; in addition, it is possible to save the current state of the simulation and continue with the execution of the simulation later. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. III44009]