An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and w...

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Bibliographic Details
Main Authors: Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert, Filip Tavernier
Format: Article
Language:English
Published: MDPI AG 2018-12-01
Series:Electronics
Subjects:
CMOS
dynamic comparator
offset calibration
high speed
low noise
low power
ADC
Online Access:http://www.mdpi.com/2079-9292/8/1/13

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