| Summary: | This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic. The complete transformation from a static ternary design into its dynamic form is comprehensively investigated. The proposed dynamic strategy does not suffer from any race or charge sharing problems. These dynamic logic problems are dealt with in this study. In addition, the number of successive pass-transistors is reduced by a design technique which shortens the critical path of ternary circuits. The new adder cells are simulated by using Synopsys HSPICE and 32 nm carbon nanotube field-effect transistor technology. Simulation results demonstrate the superiority of dynamic ternary circuits. The proposed dynamic ternary half adder operates 21% faster, consumes 23% less power, and has even 14 fewer transistors than its static counterpart.
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