Power-Clock-Gating in adiabatischen Logikschaltungen

Power-Clock-Gating in adiabatischen Logikschaltungen

In statischen CMOS-Schaltungen wird Clock-Gating verwendet, um inaktive Schaltungsgruppen abzuschalten und damit dynamische Verluste zu reduzieren. Leckströme gewinnen in den neuen Technologien zunehmend an Bedeutung, und statische Verluste treten auf, die durch Power-Gating reduziert werden. Da adi...

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Bibliographic Details
Main Authors:	Ph. Teichmann, J. Fischer, E. Amirante, D. Schmitt-Landsiedel
Format:	Article
Language:	deu
Published:	Copernicus Publications 2006-01-01
Series:	Advances in Radio Science
Online Access:	http://www.adv-radio-sci.net/4/275/2006/ars-4-275-2006.pdf

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