A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip ar...

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Main Authors: Zulqar Nain, Rashid Ali, Sheraz Anjum, Muhammad Khalil Afzal, Sung Won Kim
Format: Article
Language:English
Published: MDPI AG 2020-07-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/9/7/1076
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spelling doaj-d26684046a484015b5191ddfa1673ffe2020-11-25T02:46:39ZengMDPI AGElectronics2079-92922020-07-0191076107610.3390/electronics9071076A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip DesignsZulqar Nain0Rashid Ali1Sheraz Anjum2Muhammad Khalil Afzal3Sung Won Kim4Department of Information and Communication Engineering, Yeungnam University, Gyeongsan 38541, KoreaSchool of Intelligent Mechatronics Engineering, Sejong University, Seoul 05006, KoreaDepartment of Computer Science, COMSATS University Islamabad, Wah Campus, Wah Cantt 47040, PakistanDepartment of Computer Science, COMSATS University Islamabad, Wah Campus, Wah Cantt 47040, PakistanDepartment of Information and Communication Engineering, Yeungnam University, Gyeongsan 38541, KoreaScalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.https://www.mdpi.com/2079-9292/9/7/1076fault-tolerant routingsystem on a chip (SOC)congestion awarenessnetwork on a chip (NoC)load balancing
collection DOAJ
language English
format Article
sources DOAJ
author Zulqar Nain
Rashid Ali
Sheraz Anjum
Muhammad Khalil Afzal
Sung Won Kim
spellingShingle Zulqar Nain
Rashid Ali
Sheraz Anjum
Muhammad Khalil Afzal
Sung Won Kim
A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
Electronics
fault-tolerant routing
system on a chip (SOC)
congestion awareness
network on a chip (NoC)
load balancing
author_facet Zulqar Nain
Rashid Ali
Sheraz Anjum
Muhammad Khalil Afzal
Sung Won Kim
author_sort Zulqar Nain
title A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
title_short A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
title_full A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
title_fullStr A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
title_full_unstemmed A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
title_sort network adaptive fault-tolerant routing algorithm for demanding latency and throughput applications of network-on-a-chip designs
publisher MDPI AG
series Electronics
issn 2079-9292
publishDate 2020-07-01
description Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.
topic fault-tolerant routing
system on a chip (SOC)
congestion awareness
network on a chip (NoC)
load balancing
url https://www.mdpi.com/2079-9292/9/7/1076
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