A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools sh...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/942930 |
| Summary: | Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a
changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement
of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually
instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of
boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered
due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows
for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions.
This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4
FPGAs. The system architecture will also be presented to provide a realistic application example. |
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| ISSN: | 1687-7195 1687-7209 |