Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

• Main Authors: Hyangwoo Kim, Hyeonsu Cho, Byoung Don Kong, Jin-Woo Kim, Meyya Meyyappan, Chang-Ki Baek
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Open Journal of Nanotechnology
• Subjects: DRAM Chips; thyristor applications; memory architecture; semiconductor devices; semiconductor device modeling
• Online Access: https://ieeexplore.ieee.org/document/9285172/

Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time (Tret). For high device scalability and low program voltage (VP), lengths of the storage regions are determined by the sum of depletion widths of N- and P-storage regions. When doping concentrations of two storage regions are equal to each other at 10¹⁸ cm^-3, 2-T TRAM exhibits the longest Tret of 100 ms and the lowest impact ionization of the device can suppress various reliability issues such as hot carrier injection and junction degradation. Although Tret of 2-T TRAM can be reduced from 100 ms to 1.5 ms due to decreased read voltage with operating temperature rising from 300 K to 360 K, Tret can be further improved to >10 s by applying standby voltage (Vstandby). The effective way to set minimum Vstandby is presented using the IA-VA characteristics with 1000-s fall time. Moreover, the optimal Vstandby is set to 0.60 V by considering disturbance in array operation. Consequently, the proposed design and operation guidelines can provide a pathway to realize nanoscale 2-T TRAM for capacitor-less 4F² 1T DRAM technology.