A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm<sup>2</sup>. To enable volta...

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Main Authors:	Woorham Bae, Sung-Yong Cho, Deog-Kyoon Jeong
Format:	Article
Language:	English
Published:	MDPI AG 2021-01-01
Series:	Electronics
Subjects:	CMOS PCI Express supply regulator scalability transmitter
Online Access:	https://www.mdpi.com/2079-9292/10/1/68

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spelling	doaj-cdf289f8a6a548c6a4f68b6527c8eb332021-01-03T00:00:29ZengMDPI AGElectronics2079-92922021-01-0110686810.3390/electronics10010068A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOSWoorham Bae0Sung-Yong Cho1Deog-Kyoon Jeong2Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, USASamsung Electronics, Hwaseong 445-330, KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul 08826, KoreaThis paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm<sup>2</sup>. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.https://www.mdpi.com/2079-9292/10/1/68CMOSPCI Expresssupply regulatorscalabilitytransmitter
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Woorham Bae Sung-Yong Cho Deog-Kyoon Jeong
spellingShingle	Woorham Bae Sung-Yong Cho Deog-Kyoon Jeong A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS Electronics CMOS PCI Express supply regulator scalability transmitter
author_facet	Woorham Bae Sung-Yong Cho Deog-Kyoon Jeong
author_sort	Woorham Bae
title	A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
title_short	A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
title_full	A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
title_fullStr	A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
title_full_unstemmed	A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
title_sort	1.93-pj/bit pci express gen4 phy transmitter with on-chip supply regulators in 28 nm cmos
publisher	MDPI AG
series	Electronics
issn	2079-9292
publishDate	2021-01-01
description	This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm<sup>2</sup>. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.
topic	CMOS PCI Express supply regulator scalability transmitter
url	https://www.mdpi.com/2079-9292/10/1/68
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A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

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