Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks

• Main Authors: Huan Yu, Hemanth Chalamalasetty, Madhavan Swaminathan
• Format: Article
• Language: English
• Published: IEEE 2019-01-01
• Series: IEEE Access
• Subjects: Behavioral modeling; voltage-controlled oscillator (VCO); neural network; output buffer; Verilog-A
• Online Access: https://ieeexplore.ieee.org/document/8667456/

This paper proposes augmented neural networks (AugNNs) for modeling the behavior of steady-state oscillators in time-domain. Multi-output AugNNs with the corresponding gradient scheme and training methodology are proposed for the modeling of multi-phase oscillators. Using the proposed AugNNs, a novel technique is presented for the modeling of voltage-controlled oscillators (VCOs) including I/O behavior. In the proposed AugNNs, a periodic unit is introduced to capture the relation between the instantaneous frequency and the control signal, and to provide the phase information of the oscillation, which is used to predict the oscillatory output waveforms using feed forward neural networks (FFNN). For the modeling of VCOs including output buffers, an AugNN-based model is proposed, where recurrent neural networks (RNNs) are used to capture the nonlinear dynamic current-voltage relation at the output port. The simulated data of transistor-level oscillator circuit are used to train the proposed model. As a black-box approach, the proposed model protects intellectual property (IP) and can be implemented in Verilog-A. The examples using transistor-level oscillator circuits demonstrate the effectiveness of the proposed model for time-domain analysis.