Sparse matrix-vector multiplication on network-on-chip
In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2010-12-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/8/289/2010/ars-8-289-2010.pdf |