Sparse matrix-vector multiplication on network-on-chip
In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2010-12-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/8/289/2010/ars-8-289-2010.pdf |
| Summary: | In this paper, we present an idea for performing matrix-vector
multiplication by using Network-on-Chip (NoC) architecture. In traditional IC
design on-chip communications have been designed with dedicated
point-to-point interconnections. Therefore, regular local data transfer is
the major concept of many parallel implementations. However, when dealing
with the parallel implementation of sparse matrix-vector multiplication
(SMVM), which is the main step of all iterative algorithms for solving systems
of linear equation, the required data transfers depend on the sparsity
structure of the matrix and can be extremely irregular. Using the NoC
architecture makes it possible to deal with arbitrary structure of the data
transfers; i.e. with the irregular structure of the sparse matrices. So far,
we have already implemented the proposed SMVM-NoC architecture with the size
4×4 and 5×5 in IEEE 754 single float point precision using
FPGA. |
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| ISSN: | 1684-9965 1684-9973 |