| Summary: | As burgeoning hardware security primitive, physical unclonable function (PUF) has aroused the interest of solid-state circuit community on its efficient integration into security-critical applications. This paper presents an energy efficient implementation of classic arbiter PUF design. Current-starved (CS) inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge. The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations. A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter. By limiting the drain currents of CS-inverters to achieve ZTC, the power consumption of the proposed PUF is also reduced substantially. The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process. The fabricated chips feature a compact silicon area of 3838 μm<sup>2</sup> and low energy consumption of 2.74 pJ per bit at 25 Mbps, with measured uniqueness of 46.8% and native bit error rate (BER) of 0.8%. It is worst-case BER is less than 10.46% measured over an extended ~7× temperature range and ~5× supply voltage range. These physically measured figures of merit have outperformed previously reported measurements of strong PUFs with similar linear additive delay architecture.
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