Design and Application of Counter's Interface IP Core Based on Avalon Bus
With the wide application of the NIOS II soft-core processor based on FPGA in the control field, the research of the interface IP (intellectual property) core between NIOS II's Avalon bus and peripheral is very valuable. It combines FPGA and realizes the function of encoder pulses' shaping...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IFSA Publishing, S.L.
2013-11-01
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| Series: | Sensors & Transducers |
| Subjects: | |
| Online Access: | http://www.sensorsportal.com/HTML/DIGEST/november_2013/PDF_vol_159/P_1557.pdf |