An FPGA-Based Simple RGB-HSI Space Conversion Algorithm for Hardware Image Processing

In this paper, a new, low-complexity, easy-to-implement hardware method for color space conversion between the red-green-blue (RGB) and the hue-saturation-intensity (HSI) color spaces called the simple RGB-HSI space conversion (S-SC) algorithm is proposed, which aims to provide more rapid computing...

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Bibliographic Details
Main Authors: Shuaiqing Zhi, Yani Cui, Jiaxian Deng, Wencai Du
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9204684/
Description
Summary:In this paper, a new, low-complexity, easy-to-implement hardware method for color space conversion between the red-green-blue (RGB) and the hue-saturation-intensity (HSI) color spaces called the simple RGB-HSI space conversion (S-SC) algorithm is proposed, which aims to provide more rapid computing due to the need for fewer operations. In the S-SC algorithm, we reconstruct the model of space conversion between the RGB color space and the HSI color space (RGB-HSI) by inverting the conversion from the HSI color space to the RGB color space of the traditional geometric derivation algorithm. As a result, the nonlinear model-realized RGB-HSI color space conversion by the geometric derivation algorithm is transformed into a linear conversion model, which can avoid complicated calculations such as trigonometric and inverse trigonometric functions in the color space conversion process. The model can effectively reduce the computational complexity of the algorithm and facilitate hardware implementation at the same time. To evaluate the performance of the S-SC algorithm, we first compare the S-SC algorithm with the geometric derivation algorithm from the computational complexity perspective. On this basis, we compare the S-SC algorithm with five other RGB-HSI color space conversion algorithms from the perspectives of error and conversion effect. Finally, we use the field programmable gate array (FPGA) hardware platform to analyze and verify the timing sequence and logical resource consumption and verify the effectiveness of the proposed algorithm with experimental results. We show that the S-SC algorithm achieves good performance in terms of conversion accuracy, logical unit resource occupancy, and output timing.
ISSN:2169-3536