Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices
This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2<sup>m</sup>) based on a previously modified extended Euclidean algorithm. This structure is suitable for fixed size processor that only reuse the core and...
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2016-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/7782358/ |
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doaj-bcb39b794aec4ecdad1cb84a90e1670d2021-03-29T19:48:46ZengIEEEIEEE Access2169-35362016-01-0149758976310.1109/ACCESS.2016.26390397782358Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power DevicesAtef Ibrahim0https://orcid.org/0000-0002-1115-4051Turki F. Al-Somani1Fayez Gebali2Department of Computer Engineering, Prince Sattam Bin Abdulaziz University, Al-Kharj, Saudi ArabiaDepartment of Computer Engineering, Umm Al-Qura University, Mecca, Saudi ArabiaDepartment of Electrical and Computer Engineering, University of Victoria, Victoria, BC, CanadaThis paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2<sup>m</sup>) based on a previously modified extended Euclidean algorithm. This structure is suitable for fixed size processor that only reuse the core and does not require to modulate the core size when m modified. This structure is extracted by applying a nonlinear methodology that gives the designer more flexibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported efficient designs show that the proposed scalable structure achieves a significant reduction in the area ranging from 83.0% to 88.3% and also achieves a significant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identification (RFID) devices.https://ieeexplore.ieee.org/document/7782358/Scalable systolic arrayshardware securityfinite field inversionultra-low power devicesASIC |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Atef Ibrahim Turki F. Al-Somani Fayez Gebali |
| spellingShingle |
Atef Ibrahim Turki F. Al-Somani Fayez Gebali Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices IEEE Access Scalable systolic arrays hardware security finite field inversion ultra-low power devices ASIC |
| author_facet |
Atef Ibrahim Turki F. Al-Somani Fayez Gebali |
| author_sort |
Atef Ibrahim |
| title |
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices |
| title_short |
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices |
| title_full |
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices |
| title_fullStr |
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices |
| title_full_unstemmed |
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices |
| title_sort |
efficient scalable digit-serial inverter over gf( $2^{m}$ ) for ultra-low power devices |
| publisher |
IEEE |
| series |
IEEE Access |
| issn |
2169-3536 |
| publishDate |
2016-01-01 |
| description |
This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2<sup>m</sup>) based on a previously modified extended Euclidean algorithm. This structure is suitable for fixed size processor that only reuse the core and does not require to modulate the core size when m modified. This structure is extracted by applying a nonlinear methodology that gives the designer more flexibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported efficient designs show that the proposed scalable structure achieves a significant reduction in the area ranging from 83.0% to 88.3% and also achieves a significant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identification (RFID) devices. |
| topic |
Scalable systolic arrays hardware security finite field inversion ultra-low power devices ASIC |
| url |
https://ieeexplore.ieee.org/document/7782358/ |
| work_keys_str_mv |
AT atefibrahim efficientscalabledigitserialinverterovergf2mforultralowpowerdevices AT turkifalsomani efficientscalabledigitserialinverterovergf2mforultralowpowerdevices AT fayezgebali efficientscalabledigitserialinverterovergf2mforultralowpowerdevices |
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1724195656823734272 |