Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application

Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application

This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements...

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Bibliographic Details
Main Authors: Oleksandr Drozd, Grzegorz Nowakowski, Anatoliy Sachenko, Viktor Antoniuk, Volodymyr Kochan, Myroslav Drozd
Format: Article
Language:English
Published: MDPI AG 2021-01-01
Series:Sensors
Subjects:
safety-related system
component
FPGA-designing
logical and power-oriented checkability
hidden faults
clock signal
Online Access:https://www.mdpi.com/1424-8220/21/3/792

Internet

https://www.mdpi.com/1424-8220/21/3/792

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