Interfaz programable de comunicación serie asincrónica en FPGA

• Main Authors: Berta Pallerols Mir, Rubén D. López Noa, Roger Rivero Labrada, Danelia Matos Molina, Alexander Suárez Léon
• Format: Article
• Language: Spanish
• Published: Instituto Superior Politécnico José Antonio Echeverría (CUJAE) 2010-09-01
• Series: Revista Ingeniería Electrónica, Automática y Comunicaciones
• Online Access: http://rielac.cujae.edu.cu/index.php/rieac/article/view/42

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mso-pagination:widow-orphan;&#13; font-size:11.0pt;&#13; font-family:"Calibri","sans-serif";&#13; mso-ascii-font-family:Calibri;&#13; mso-ascii-theme-font:minor-latin;&#13; mso-fareast-font-family:"Times New Roman";&#13; mso-fareast-theme-font:minor-fareast;&#13; mso-hansi-font-family:Calibri;&#13; mso-hansi-theme-font:minor-latin;&#13; mso-bidi-font-family:"Times New Roman";&#13; mso-bidi-theme-font:minor-bidi;}&#13; </style> <![endif]--> <p class="Textonormal"><span lang="ES">El presente artículo muestra el diseño, implementación y prueba de una interfaz programable de comunicación serie asincrónica en un FPGA. El diseño está orientado a emular de forma parcial el funcionamiento de los dispositivos de recepción – transmisión asincrónica universal (UART) comerciales del fabricante Intel®. Se muestra la estructura interna de los bloques funcionales fundamentales y los resultados de la simulación funcional. Finalmente algunas aplicaciones y los principales aspectos distintivos del diseño son discutidos.</span></p>