DESIGN OF FIVE PORT PRIORITY BASED ROUTER WITH PORT SELECTION LOGIC FOR NoC
Network-on-chip (NoC) is a relatively new technology to signaling that enables not only more efficient interconnects but also more efficient design and verification processes for modern SoCs. The communication through the NoC is performed by enabling processing element (PE) to send and receive p...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2017-01-01
|
| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_2_Iss_4_Paper_1_293_299.pdf |
| Summary: | Network-on-chip (NoC) is a relatively new technology to signaling that
enables not only more efficient interconnects but also more efficient
design and verification processes for modern SoCs. The communication
through the NoC is performed by enabling processing element (PE) to
send and receive packets through the network fabric composed of
switches/routers connected together through physical links or channels.
For effective global on-chip communication, routers provide efficient
routing with comparatively low complexity and high performance.
Communication deadlock may appear at the router network and can
cause performance degradation and system failure. Based on these
studies, a five port priority based router is proposed. Port selection logic
is used for selecting the ports for data transmission to selective ports.
The proposed router shows better performance when tested in Mesh and
Torus topology. Round Robin Algorithm is used in arbiter, which
handles the process with priority and has low power consumption. The
designed router is implemented in Artix 7, Spartan 6 and Virtex 7 using
Xilinx ISE 14.7 design tool and power consumption of five port router
is taken in Synopsis VHDL and power compiler tool |
|---|---|
| ISSN: | 2395-1672 2395-1680 |