| Summary: | To achieve high computation throughput, heterogeneous architectures utilize many special-purpose cores to work as floating point computing coprocessors. Popular programming models typically offload computing intensive operations to coprocessors and then aggregate the results. This approach results in the need of transferring a large amount of data via the peripheral component interconnect express (PCIe). To leverage the limited bandwidth of PCIe, we develop a reverse offload (rOffload) model that treats the autonomous Intel Many Integrated Core (MIC) coprocessor as the host processor while the CPU is treated as the coprocessor. The MICs orchestrate the computation and offload work, which cannot be accelerated on MIC, to the CPUs, thus reducing the overhead introduced by moving data among distinct memory regions. In this paper, we present an overview of rOffload, including the basic programming interface and its implementation on a CPU-MIC system. The results from benchmarking and from application experiments conducted on the Tianhe-2 supercomputer demonstrate the efficiency of our rOffload model in terms of programmability, portability, and performance.
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