A Coarse-Fine Time-to-Digital Converter
A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized the dual DLL structure to achieve high precis...
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| Format: | Article |
| Language: | English |
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EDP Sciences
2017-01-01
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| Series: | ITM Web of Conferences |
| Online Access: | https://doi.org/10.1051/itmconf/20171108006 |
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Article |
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doaj-b324cc42f55f49d196f77bb1e51407752021-02-02T06:16:46ZengEDP SciencesITM Web of Conferences2271-20972017-01-01110800610.1051/itmconf/20171108006itmconf_ist2017_08006A Coarse-Fine Time-to-Digital ConverterChen Ya-QianMeng Li-YaLin Xiao-GangA design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized the dual DLL structure to achieve high precision. The proposed TDC can provide high resolution with less chip area. With an input reference clock of 125MHZ, the TDC achieves 8ps resolution, and the dynamic range achieves 1.5μs.https://doi.org/10.1051/itmconf/20171108006 |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Chen Ya-Qian Meng Li-Ya Lin Xiao-Gang |
| spellingShingle |
Chen Ya-Qian Meng Li-Ya Lin Xiao-Gang A Coarse-Fine Time-to-Digital Converter ITM Web of Conferences |
| author_facet |
Chen Ya-Qian Meng Li-Ya Lin Xiao-Gang |
| author_sort |
Chen Ya-Qian |
| title |
A Coarse-Fine Time-to-Digital Converter |
| title_short |
A Coarse-Fine Time-to-Digital Converter |
| title_full |
A Coarse-Fine Time-to-Digital Converter |
| title_fullStr |
A Coarse-Fine Time-to-Digital Converter |
| title_full_unstemmed |
A Coarse-Fine Time-to-Digital Converter |
| title_sort |
coarse-fine time-to-digital converter |
| publisher |
EDP Sciences |
| series |
ITM Web of Conferences |
| issn |
2271-2097 |
| publishDate |
2017-01-01 |
| description |
A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized the dual DLL structure to achieve high precision. The proposed TDC can provide high resolution with less chip area. With an input reference clock of 125MHZ, the TDC achieves 8ps resolution, and the dynamic range achieves 1.5μs. |
| url |
https://doi.org/10.1051/itmconf/20171108006 |
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AT chenyaqian acoarsefinetimetodigitalconverter AT mengliya acoarsefinetimetodigitalconverter AT linxiaogang acoarsefinetimetodigitalconverter AT chenyaqian coarsefinetimetodigitalconverter AT mengliya coarsefinetimetodigitalconverter AT linxiaogang coarsefinetimetodigitalconverter |
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1724301654691414016 |