Triple frame buffer FPGA implementation
This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of t...
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Online Access: | http://www.sciencedirect.com/science/article/pii/S2468067218300798 |
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doaj-b052fedbb902496690624ffca06f42012020-11-25T02:17:21ZengElsevierHardwareX2468-06722019-04-015Triple frame buffer FPGA implementationJames Williams0Ilya Mikhelson1Corresponding author.; Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, United StatesDepartment of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, United StatesThis article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool. Keywords: Verilog, FPGA, Hardware description, Frame buffer, Camera, Educationhttp://www.sciencedirect.com/science/article/pii/S2468067218300798 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
James Williams Ilya Mikhelson |
spellingShingle |
James Williams Ilya Mikhelson Triple frame buffer FPGA implementation HardwareX |
author_facet |
James Williams Ilya Mikhelson |
author_sort |
James Williams |
title |
Triple frame buffer FPGA implementation |
title_short |
Triple frame buffer FPGA implementation |
title_full |
Triple frame buffer FPGA implementation |
title_fullStr |
Triple frame buffer FPGA implementation |
title_full_unstemmed |
Triple frame buffer FPGA implementation |
title_sort |
triple frame buffer fpga implementation |
publisher |
Elsevier |
series |
HardwareX |
issn |
2468-0672 |
publishDate |
2019-04-01 |
description |
This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool. Keywords: Verilog, FPGA, Hardware description, Frame buffer, Camera, Education |
url |
http://www.sciencedirect.com/science/article/pii/S2468067218300798 |
work_keys_str_mv |
AT jameswilliams tripleframebufferfpgaimplementation AT ilyamikhelson tripleframebufferfpgaimplementation |
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1724886835938721792 |