Triple frame buffer FPGA implementation
This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of t...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2019-04-01
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| Series: | HardwareX |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2468067218300798 |