One approach to compact testing of digital circuits

A problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vecto...

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Main Author: Feofanovich Berezkin Evgeniy
Format: Article
Language:English
Published: Institut za istrazivanja i projektovanja u privredi 2019-01-01
Series:Istrazivanja i projektovanja za privredu
Subjects:
Online Access:https://scindeks-clanci.ceon.rs/data/pdf/1451-4117/2019/1451-41171901026F.pdf
id doaj-ac93037e01da40208b61795c6c1ea174
record_format Article
spelling doaj-ac93037e01da40208b61795c6c1ea1742021-04-02T12:29:47ZengInstitut za istrazivanja i projektovanja u privrediIstrazivanja i projektovanja za privredu1451-41171821-31972019-01-0117126341451-41171901026FOne approach to compact testing of digital circuitsFeofanovich Berezkin Evgeniy0National Research Nuclear University "MEPhI", Institute of Cyber Intelligence Systems, Department of Computer Systems and Technologies, Moscow, Russian FederationA problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vectors or matrices resulting from failures of diagnostics objects related to the postulated class. Any other error vectors or matrices can be non-detectable and are excluded from consideration. For the compact testing of separate units of complex digital systems, the problem of synthesis of the generator structure that reproduces an assigned sequence of binary sets is being solved. Increased attention is given to issues of the non-excessive reproduction of sets sequence and structural organization simplicity. The solution is based on the application of a mathematical tool for linear sequence machines. A software implementation of the mathematical model is proposed. Error vectors or matrix detection process visualization AIDS are given. Additionally, means of the binary sets generation process visualization are presented.https://scindeks-clanci.ceon.rs/data/pdf/1451-4117/2019/1451-41171901026F.pdfvectortestssynthesissequencingmatricesdigitizationcompactnessapproach
collection DOAJ
language English
format Article
sources DOAJ
author Feofanovich Berezkin Evgeniy
spellingShingle Feofanovich Berezkin Evgeniy
One approach to compact testing of digital circuits
Istrazivanja i projektovanja za privredu
vector
tests
synthesis
sequencing
matrices
digitization
compactness
approach
author_facet Feofanovich Berezkin Evgeniy
author_sort Feofanovich Berezkin Evgeniy
title One approach to compact testing of digital circuits
title_short One approach to compact testing of digital circuits
title_full One approach to compact testing of digital circuits
title_fullStr One approach to compact testing of digital circuits
title_full_unstemmed One approach to compact testing of digital circuits
title_sort one approach to compact testing of digital circuits
publisher Institut za istrazivanja i projektovanja u privredi
series Istrazivanja i projektovanja za privredu
issn 1451-4117
1821-3197
publishDate 2019-01-01
description A problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vectors or matrices resulting from failures of diagnostics objects related to the postulated class. Any other error vectors or matrices can be non-detectable and are excluded from consideration. For the compact testing of separate units of complex digital systems, the problem of synthesis of the generator structure that reproduces an assigned sequence of binary sets is being solved. Increased attention is given to issues of the non-excessive reproduction of sets sequence and structural organization simplicity. The solution is based on the application of a mathematical tool for linear sequence machines. A software implementation of the mathematical model is proposed. Error vectors or matrix detection process visualization AIDS are given. Additionally, means of the binary sets generation process visualization are presented.
topic vector
tests
synthesis
sequencing
matrices
digitization
compactness
approach
url https://scindeks-clanci.ceon.rs/data/pdf/1451-4117/2019/1451-41171901026F.pdf
work_keys_str_mv AT feofanovichberezkinevgeniy oneapproachtocompacttestingofdigitalcircuits
_version_ 1721568765164912640