Pipelined Error-detecting Codes in FPGA Testing
This article approaches the solution of FPGA testing and research of characteristics at early development stages. The approach offers error-detection code based on universal test firmware. The performed test firmware based on CRC and Hamming codes detect single and multiple faults, and locate fa...
Main Authors: | BREKHOV, O., RATNIKOV, M. |
---|---|
Format: | Article |
Language: | English |
Published: |
Stefan cel Mare University of Suceava
2014-05-01
|
Series: | Advances in Electrical and Computer Engineering |
Subjects: | |
Online Access: | http://dx.doi.org/10.4316/AECE.2014.02010 |
Similar Items
-
Signature and Residue Testing of Microprogrammable Control Units
by: Vadim Geurkov
Published: (2016-01-01) -
Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation
by: Weigang Chen, et al.
Published: (2020-01-01) -
A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
by: Peter Hailes, et al.
Published: (2017-01-01) -
A Form of List Viterbi Algorithm for Decoding Convolutional Codes
by: Shamsuddeen Hassan Muhammad, et al.
Published: (2018-10-01) -
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction
by: Valentina Bianchi, et al.
Published: (2020-02-01)