A Card Stack Model to Elucidate Key Challenges in the Development of Future Generation Supercomputers

• Main Author: Wataru Nakayama
• Format: Article
• Language: English
• Published: IEEE 2013-01-01
• Series: IEEE Access
• Subjects: Computational efficiency; computational density; dielectric coolant; immersion cooling; hardware; supercomputer
• Online Access: https://ieeexplore.ieee.org/document/6552991/

This paper intends to elucidate challenges in some aspects of the hardware design of future generation computers. We use a system model, a stack of integrated circuit cards cooled by a dielectric coolant (FC77). A set of equations is developed to describe the relationships between the system throughput, the volume, the power consumption, and those concerning the details of internal organization such as signal and power line dimensions and coolant path width. The calculated values of throughput, volume, and power are projected on a state point in a graph of the figures-of-merit pair, the computational density, and the computational efficiency. By manipulating the empirical parameters imbedded in the model, the state point is steered to follow the evolutionary line that runs through the points corresponding to the existing supercomputers of several generations. Then, calculation is extended on state points for future prospective computers with target system throughputs. The results point to the needs for research and development effort on thermal management and materials development. As for thermal management of exa- and zeta-scale computers, we need to refocus heat transfer research. Coolant channels will have very large length-to-width ratios (several thousand), while the heat flux on the channel surface is quite low. Micro-fluidics to guarantee stable coolant flow in such long micro-channels will be of primary importance in place of the means to deal with high heat flux. We also need to develop novel materials for signal transmission lines and cooling, particularly in the development of zeta-scale computers.