Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

• Main Authors: Yuanjun Cen, Wei Feng, Ping Yang, Hua Fan, Yongkai Li, Yi Niu, Zhikai Liao, Xu Qi, Bo Wang, Yan Ran, Wei Li, Quanyuan Feng, Hadi Heidari
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: Segmented capacitor array; SAR ADC; linearity error; calibration
• Online Access: https://ieeexplore.ieee.org/document/9200325/
• ISSN: 2169-3536

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6μm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.