Pulse width control loop as a duty cycle corrector
The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system’s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buf...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Faculty of Technical Sciences in Cacak
2004-01-01
|
| Series: | Serbian Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | http://www.doiserbia.nb.rs/img/doi/1451-4869/2004/1451-48690402215J.pdf |