An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclo...

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Bibliographic Details
Main Authors: Zhipeng Song, Zhixiang Zhao, Hongsen Yu, Jingwu Yang, Xi Zhang, Tengjie Sui, Jianfeng Xu, Siwei Xie, Qiu Huang, Qiyu Peng
Format: Article
Language:English
Published: MDPI AG 2020-04-01
Series:Sensors
Subjects:
time-to-digital converter (TDC)
field-programmable gate arrays (FPGA)
non-uniform multiphase (NUMP) method
temperature correction
Online Access:https://www.mdpi.com/1424-8220/20/8/2172

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https://www.mdpi.com/1424-8220/20/8/2172

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