Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) struc...

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Bibliographic Details
Main Authors: William Cheng-Yu Ma, Yan-Jia Huang, Po-Jen Chen, Jhe-Wei Jhu, Yan-Shiuan Chang, Ting-Hsuan Chang
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Monolithic 3D-IC
nanosheet channel
low power
thin-film transistor
Online Access:https://ieeexplore.ieee.org/document/9141258/

Internet

https://ieeexplore.ieee.org/document/9141258/

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