Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis
The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP pro...
Main Authors: | Anirban Sengupta, Saumya Bhadauria |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2016-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/7448836/ |
Similar Items
-
Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis
by: Anirban Sengupta, et al.
Published: (2017-04-01) -
Evaluation Techniques for Mapping IPs on FPGAs
by: Lakshminarayana, Avinash
Published: (2014) -
A framework for automation of system-level design space exploration
by: Kathuria, Manan
Published: (2012) -
Ownership protection of outsourced biomedical time series data based on optimal watermarking scheme in data mining
by: Trung Duy Pham, et al.
Published: (2017-11-01) -
Using Design Science to build a Watermark System for Righful Ownership Protection in the Cloud
by: Cusack, B, et al.
Published: (2017)