Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

• Main Authors: Anirban Sengupta, Saumya Bhadauria
• Format: Article
• Language: English
• Published: IEEE 2016-01-01
• Series: IEEE Access
• Subjects: IPSecurity; Watermark; Design abstraction; High level synthesis; Design space exploration; Particle swarm optimization
• Online Access: https://ieeexplore.ieee.org/document/7448836/

The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP protection for anti-piracy as an important subject of research for a system design. Watermarking is expected to provide the best protection of authorship when applied at higher levels, i.e., during high-level synthesis. It is also well acknowledged that watermark insertion is non-trivial, as it is very difficult to choose a strong signature that results in higher security and less area overhead among available design solutions. This paper presents a novel multi-variable signature encoding for embedding a dynamic watermark in an IP design during architectural synthesis that provides enhanced security against typical attacks. Owing to the involvement of multiple (four) variables in the proposed signature, it is difficult to realize the signature without complete encoding knowledge of the four variables. Second, our approach aims to optimize the embedding cost of the watermark by exploring a low-cost solution through particle swarm optimization-driven design space exploration based on area-delay constraints. Comparison with a recent technique indicated that our watermark incurs lower embedding cost, lower runtime, and less storage hardware.