| Summary: | There is no doubt that static complementary CMOS logic is one of the most dominant logic-circuit families available. However, CMOS circuits with wide fan-in suffer from a relatively poor performance that is apparent in increased area, large time delay, and large power consumption. This is typically the case with CMOS circuits containing NMOS or PMOS stacks (i.e. branches containing a relatively large number of serially connected transistors). In this paper, a novel circuit that depends on applying the input signals in the form of pulses with a certain width will be presented as an alternative to stack circuits. The proposed scheme will be investigated quantitatively with the effect of the pulse width on the performance of the proposed scheme taken into account. The proposed scheme will be compared with the conventional CMOS logic from the points of view of area, high-to-low propagation delay, and average power consumption. The parameter variations and second-order effects will also be taken into account. Simulation results verify the correct operation of the proposed scheme and that the percentage reduction in the average propagation delay is 15.8% and 61.25% in cases of four and eight inputs, respectively, adopting the 45 nm CMOS technology with VDD = 1 V.
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