System-Level Leakage Power Estimation Model for ASIC Designs
With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In t...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
VSB-Technical University of Ostrava
2018-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/2947 |