System-Level Leakage Power Estimation Model for ASIC Designs
With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In t...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
VSB-Technical University of Ostrava
2018-01-01
|
| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/2947 |
| Summary: | With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In this paper, we present the power estimation models for ASIC (Application Specific Integrated Circuit) based designs at the C-level of abstraction. The method includes analysis and extraction of the application specific information from the LLVM (Low-Level Virtual Machine) bit-code; which further applies to train the neural network. The trained model is applied in the estimation of the leakage power. Estimation of design power using our models is compared to the implemented measurement, which demonstrates its accuracy. In addition, the proposed methodology is significantly quicker and abolishes the need of synthesis based exploration. |
|---|---|
| ISSN: | 1336-1376 1804-3119 |