Reducing the Delay for Decoding Instructions by Predicting Their Source Register Operands
The fetched instructions would have data dependency with in-flight ones in the pipeline execution of a processor, so the dependency prevents the processor from executing the incoming instructions for guaranteeing the program’s correctness. The register and memory dependencies are detected in the dec...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-05-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/9/5/820 |