An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations
In standard computing architectures, memory and logic circuits are separated, a feature that slows matrix operations vital to deep learning algorithms. Here, the authors present an alternate in-memory architecture and demonstrate a feasible approach for analog matrix multiplication.
| Main Authors: | , , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Nature Publishing Group
2021-06-01
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| Series: | Nature Communications |
| Online Access: | https://doi.org/10.1038/s41467-021-23719-3 |