A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching...
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MDPI AG
2020-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/7/1100 |
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doaj-94e185cd5d6c4a88b243185721ccfdf72020-11-25T02:53:19ZengMDPI AGElectronics2079-92922020-07-0191100110010.3390/electronics9071100A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC ApplicationDeeksha Verma0Khuram Shehzad1Danial Khan2Sung Jin Kim3Young Gun Pu4Sang-Sun Yoo5Keum Cheol Hwang6Youngoo Yang7Kang-Yoon Lee8College of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Seoul 16419, KoreaA design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CV<sub>REF</sub><sup>2</sup> switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.https://www.mdpi.com/2079-9292/9/7/1100asynchronous comparator clock generationasynchronous successive approximation register (SAR) ADCcapacitive DAC (CDAC)low power consumption |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Deeksha Verma Khuram Shehzad Danial Khan Sung Jin Kim Young Gun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| spellingShingle |
Deeksha Verma Khuram Shehzad Danial Khan Sung Jin Kim Young Gun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application Electronics asynchronous comparator clock generation asynchronous successive approximation register (SAR) ADC capacitive DAC (CDAC) low power consumption |
| author_facet |
Deeksha Verma Khuram Shehzad Danial Khan Sung Jin Kim Young Gun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| author_sort |
Deeksha Verma |
| title |
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application |
| title_short |
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application |
| title_full |
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application |
| title_fullStr |
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application |
| title_full_unstemmed |
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application |
| title_sort |
design of low-power 10-bit 1-ms/s asynchronous sar adc for dsrc application |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2020-07-01 |
| description |
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CV<sub>REF</sub><sup>2</sup> switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply. |
| topic |
asynchronous comparator clock generation asynchronous successive approximation register (SAR) ADC capacitive DAC (CDAC) low power consumption |
| url |
https://www.mdpi.com/2079-9292/9/7/1100 |
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